OpenBikeComputer
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Display protocol

The device uses a Sharp LS021B7DD02 reflective memory-in-pixel LCD of 240 × 320 pixels. Every subpixel has a one-bit latch on the glass, so the panel keeps its image with no scan traffic. That is the property the device is built around: a map left on the screen costs almost nothing. The framebuffer is RGB222, which is four levels per channel and 64 colors.

Two signal paths

Two independent signal paths Path A · image write — intermittent gate scan GSP · GCK · GEN · INTB source shift BSP · BCK · R/G/B[0:1] write 1 bit subpixel latch one bit, on glass held without a scan selects a rail Path B · polarity — ~60 Hz VCOM VB VA VB in phase with VCOM · VA inverse → drives the LC (never DC)
Path A writes the pixel latches. Path B continuously drives the liquid crystal at approximately 60 Hz. A stored bit selects the VA or VB rail.

Writing an image and driving the liquid crystal are separate. The write is intermittent and pushes one bit into each subpixel latch. The polarity waveform is continuous, and the stored bit selects which rail the subpixel follows.

Never stop that waveform while the panel has power: a liquid crystal held at a DC bias is damaged. A hardware timer generates it, so a busy or sleeping processor cannot interrupt it.

Pixel encoding

One pixel cell — three stacked bands R G B MSB band LSB band MSB band MSB plane 2/3 area · top + bottom LSB plane 1/3 area · middle
The connected MSB bands cover two-thirds of the subpixel. The LSB band covers one-third. The two bits give four visible levels.

The panel makes four levels per channel by area: each subpixel has a large block and a small block, two thirds and one third of its area. The two bits of a channel are those two blocks, so a level needs no lookup table.

Gate scan

One pixel row = one GCK period GCK MSB phase · GCK HIGH shift MSB plane → 2/3 block LSB phase · GCK LOW shift LSB plane → 1/3 block GEN latch 2/3 latch 1/3 advance + MSB next row one gate advance per pixel row · two GEN pulses per row
Send the MSB plane while GCK is high. Send the LSB plane while GCK is low. Pulse GEN after each plane.

A row is written in one clock period, in two phases: the larger block while the clock is high and the smaller while it is low, with a latch pulse after each. One period advances one row. A frame raises the envelope signal, writes the rows, and drops it again; with the envelope low the panel holds what it has.

Partial update

The presenter compares row hashes and sends only the changed row spans. The scan advances past unchanged rows without latching them and stops after the last changed row, so a frame costs what changed and not what the screen holds. That is how a clock digit costs a few rows.

Power-on, power-off, and retention

Write a black frame at power-on, settle, then start the waveform. Write the safe state at power-off before the waveform stops. Refresh a static image at least every two days.

Timing

The signal names, their rails, and every timing limit are the panel datasheet's, and the implementation holds them in one place: the wire packer builds the bus words, the COM driver makes the polarity waveform, and the scan program runs on the coprocessor that writes the panel.

The current scan clocks the source bus faster than the datasheet maximum. It passed a visual test on one panel at room temperature, which is not production validation.

Panel power follows the update rate, and partial updates are what keep the average near the cost of holding an image.

Implementation